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| document number: MC33580 rev. 6.0, 4/2007 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007. all rights reserved. quad high-side switch (quad 15 m ? ) the 33580 is one in a family of devices designed for low-voltage automotive and industrial lighting and motor control applications. its four low r ds(on) mosfets (four 15 m ? ) can control the high sides of four separate resistive or inductive loads. programming, control, and diagnostics are accomplished using a 16-bit spi interface. additionally, eac h output has its own parallel input for pulse-width modulation (pwm) control if desired. the 33580 allows the user to program via the spi the f ault current trip levels and duration of acceptable lamp inrush or motor stall intervals. such programmability allows tight control of fault currents and can protect wiring harnesses and circuit boards as well as loads. the 33580 is packaged in a power-enhanced 12 x 12 nonleaded power qfn package with exposed tabs. features ?quad 15 m ? high-side switches (at 25c) ? operating voltage range of 6.0 v to 27 v with standby current < 5.0 a ? spi control of overcurrent limit, overcurrent fault blanking time, output off open load detection, output on / off control, watchdog timeout, slew rates, and fault status reporting ? spi status reporting of overcurrent, open and shorted loads, overtemperature, undervolta ge and overvoltage shutdown, fail-safe pin status, and program status ? analog current feedback with selectable ratio ? analog board temperature feedback ? enhanced -16 v reverse polarity v pwr protection ? pb-free packaging designated by suffix code pna figure 1. 33580 simplified application diagram high-side switch pna suffix (pb-free) 98art10510d 24-pin pqfn (12 x 12) 33580 ordering information device temperature range (t a ) package MC33580bapna/r2 - 40c to 125c 24 pqfn vdd so sclk cs si i/o i/o i/o i/o i/o i/o vpwr wake si sclk cs so rst fs in0 in1 in2 in3 gnd hs0 hs1 gnd load 0 33580 mcu v dd v dd v dd v pwr a/d a/d gnd csns temp fsi v pwr load 1 load 2 load 3 hs2 hs3
analog integrated circuit device data 2 freescale semiconductor 33580 block diagram block diagram figure 2. 33580 simplifi ed internal block diagram gnd programmable watchdog 279 ms?2250 ms overtemperature detection logic spi 3.0 mhz selectable over- hs[0:3]: 4.8 a?18.2 a selectable overcurrent internal regulator selectable slew rate gate drive over/undervoltage protection hs0 vpwr vdd cs sclk so si rst wake fs in0 fsi in3 hs1 hs0 hs1 hs2 hs3 hs2 hs3 in1 in2 current low detection hs[0:3]: 70 a or 100 a selectable output current hs[0:3]: 1/13000 or 1/38000 csns recopy (analog mux) v ic v ic i dwn i up i dwn r dwn open load detection high detection selectable over- current low detection 0.15 ms?155 ms blanking time temperature feedback temp v ic analog integrated circuit device data freescale semiconductor 3 33580 pin connections pin connections figure 3. 33580 pin connections table 1. 33580 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 16 . pin number pin name pin function formal name definition 1 csns output output current monitoring the current sense pin sources a current proportional to the designated hs0 : hs3 output. 2 3 5 6 in0 in1 in2 in3 input serial inputs the in0 : in3 high-side input pins are us ed to directly control hs0 : hs3 high- side output pins, respectively. 4 temp output temperature feedback this pin reports an analog value proporti onal to the temperature of the gnd flag (pins 14, 17, 23). it is used by the mcu to monitor board temperature. 7 fs output fault status (active low) this pin is an open drain configured outpu t requiring an external pullup resistor to v dd for fault reporting. 8 wake input wake this input pin controls the devic e mode and watchdog timeout feature if enabled. 9 rst input reset this input pin is used to initialize t he device configuration and fault registers, as well as place the device in a low-current sleep mode. 10 cs input chip select (active low) this input pin is connected to a chip se lect output of a master microcontroller (mcu). 11 sclk input serial clock this input pin is connected to the mcu pr oviding the required bit shift clock for spi communication. 12 si input serial input this pin is a command data input pin connected to the spi serial data output of the mcu or to the so pin of the previous device of a daisy - chain of devices. transparent top view of package 13 24 12 1098 7654 321 11 23 22 19 20 21 16 17 18 15 14 so gnd hs3 hs1 nc hs0 hs2 gnd fsi vdd si sclk cs rst wake fs in3 in2 temp in1 in0 csns gnd vpwr analog integrated circuit device data 4 freescale semiconductor 33580 pin connections 13 vdd power digital drain voltage (power) this pin is an external voltage input pi n used to supply power to the spi circuit. 14, 17, 23 gnd ground ground these pins are the ground for the logi c and analog circuitry of the device. 15 vpwr power positive power supply this pin connects to the positive power supply and is the source of operational power for the device. 16 so output serial output this output pin is connected to the spi se rial data input pin of the mcu or to the si pin of the next device of a daisy - chain of devices. 18 19 21 22 hs3 hs1 hs0 hs2 output high-side outputs protected 15 m ? high-side power output pins to the load. 20 nc n/a no connect this pin may not be connected. 24 fsi input fail-safe input the value of the resistance connected between this pin and ground determines the state of the outputs after a watchdog timeout occurs. table 1. 33580 pin de finitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 16 . pin number pin name pin function formal name definition analog integrated circuit device data freescale semiconductor 5 33580 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings operating voltage range steady-state v pwr(ss) -16 to 41 v v dd supply voltage v dd -0.3 to 5.5 v input / output voltage (1) see note (1) - 0.3 to 7.0 v so output voltage (1) v so - 0.3 to v dd + 0.3 v wake input clamp current i cl(wake) 2.5 ma csns input clamp current i cl(csns) 10 ma hs [0:3] voltage positive negative v hs 41 -16 v output current (2) i hs[0:3] 22.8 a output clamp energy (3) e cl [0:3] 0.2 j esd voltage (4) human body model (hbm) charge device model (cdm) corner pins (1, 13, 19, 21) all other pins (2-12, 14-18, 20, 22-24) v esd1 v esd2 2000 750 500 v thermal ratings operating temperature ambient junction t a t j - 40 to 125 - 40 to 150 c storage temperature t stg - 55 to 150 c thermal resistance (5) junction to case junction to ambient r jc r ja <1.0 30 c/ w peak pin reflow temperature during solder mounting (6) t solder 245 c notes 1. exceeding voltage limits on in[0:3], rst , fsi, csns, temp, si, so, sclk, cs , or fs pins may cause a malfunction or permanent damage to the device. 2. continuous high-side output current rating so long as maximum junc tion temperature is not exceede d. calculation of maximum ou tput current using package thermal resistance is required. 3. active clamp energy usi ng single-pulse method (l = 2 mh, r l = 0 ? , v pwr = 14 v, t j = 150 c initial). 4. esd testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ? ), the machine model (mm) (c zap = 200 pf, r zap = 0 ? ), and the charge device model (cdm), robotic (c zap = 4.0pf). 5. device mounted on a 2s2p test board per jedec jesd51-2. 6. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. analog integrated circuit device data 6 freescale semiconductor 33580 electrical characteristics static electical characteristics static electical characteristics table 3. static electric al characteristics characteristics noted under conditions 6.0 v v pwr 27 v, 4.5 v v dd 5.5 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted refl ect the approximate par ameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power input (vpwr, vdd) battery supply voltage range fully operational v pwr 6.0 ? 27 v v pwr operating supply current outputs on, hs[0 : 3] open i pwr(on) ??20 ma v pwr supply current outputs off, open load detection disabled, wake > 0.7 v dd , rst = v logic high i pwr(sby) ??5.0 ma sleep state supply current ( v pwr = 14 v, rst < 0.5 v, wake < 0.5 v) t a = 25c t a = 85c i pwr(sleep) ? ? 1.0 ? 10 50 a v dd supply voltage v dd(on) 4.5 5.0 5.5 v v dd supply current no spi communication 3.0 mhz spi communication (8) i dd(on) ? ? ? ? 1.0 5.0 ma v dd sleep state current i ddsleep ??5.0 a overvoltage shutdown threshold v ov 28 32 36 v overvoltage shutdown hysteresis v ovhys 0.2 0.8 1.5 v undervoltage shutdown threshold (7) v uv 4.75 5.25 5.75 v undervoltage hysteresis (9) v uvhys ?0.25? v undervoltage power-on reset v uvpor ? ? 4.75 v notes 7. the undervoltage fault condition is reported to spi register as long as the external vdd supply is within specification and t he vrwr voltage level does not go below the undervoltage power-on reset threshold. 8. not guaranteed in production. 9. this applies when the undervoltage fault is not latched (in[0:3] = 0). analog integrated circuit device data freescale semiconductor 7 33580 electrical characteristics static electical characteristics outputs (hs0, hs1, hs2, hs3) output drain-to-source on resistance ( i hs = 10 a, t a = 25 c) v pwr = 6.0 v v pwr = 10 v v pwr = 13 v r ds(on) ? ? ? ? ? ? 23 15 15 m ? output drain-to-source on resistance (i hs = 10 a, t a = 150 c) v pwr = 6.0 v v pwr = 10 v v pwr = 13 v r ds(on) ? ? ? ? ? ? 38 25.5 25.5 m ? output source-to-drain on resistance (10) i hs = 5.0 a, t a = 25 c, v pwr = -12 v r sd(on) ??30 m ? output overcurrent high detection levels (9.0 v < v pwr < 16 v) soch = 0 (11) soch = 1 i och0 i och1 80 56 100 70 120 84 a overcurrent low detection levels (9.0 v < v pwr < 16 v) socl[2:0] : 000 socl[2:0] : 001 socl[2:0] : 010 socl[2:0] : 011 socl[2:0] : 100 socl[2:0] : 101 socl[2:0] : 110 socl[2:0] : 111 i ocl0 i ocl1 i ocl2 i ocl3 i ocl4 i ocl5 i ocl6 i ocl7 14.6 13 11.5 10 8.4 6.9 5.4 3.8 18.2 16.3 14.4 12.5 10.5 8.6 6.7 4.8 22.8 20.4 18 15.7 13.2 10.8 8.4 6.0 a current sense ratio (9.0 v < v pwr < 16 v, csns < 4.5 v) dicr d2 = 0 dicr d2 = 1 c sr0 c sr1 ? ? 1/13000 1/38000 ? ? ? current sense ratio (c sr0 ) accuracy output current 2.0 to 10 a c sr0_acc - 15 ? 15 % current sense ratio (c sr1 ) accuracy output current 10 a to 20 a c sr1_acc - 19 ? 19 % current sense clamp voltage csns open; i hs[0:3] = 22 a v cl(csns) 4.5 6.0 7.0 v open load detection current (12) i oldc 30 ? 100 a notes 10. source-drain on resistance (reverse drain-to -source on resistance) with negative polarity v pwr . 11. guaranteed by process monitoring. 12. output off open load detection current is the current required to flow through the load for the purpose of detecting the exi stence of an open load condition when the specific output is commanded off. table 3. static electrical characteristics (continued) characteristics noted under conditions 6.0 v v pwr 27 v, 4.5 v v dd 5.5 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted refl ect the approximate par ameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit analog integrated circuit device data 8 freescale semiconductor 33580 electrical characteristics static electical characteristics outputs (hs0, hs1, hs2, hs3) (continued) output fault detection threshold output programmed off v ofd(thres) 2.0 3.0 4.0 v output negative clamp voltage 0.5 a < i hs[0:3] < 2.0 a, output off v cl - 20 ? -16 v overtemperature shutdown (13) t sd 155 175 190 c overtemperature shutdown hysteresis (13) t sd(hys) 5.0 ? 20 c control interface (sclk, si, so, in[0:3], rst , wake, fs , cs , fsi) input logic high voltage (14) v ih 0.7 v dd ? ? v input logic low voltage (14) v il ? ? 0.2 v dd v input logic voltage hysteresis (15) v in(hys) 100 850 1200 mv input logic pulldown current (sclk, si, in[0:3], vin>0.2 vdd) i dwn 5.0 ? 20 a rst input voltage range v rst 4.5 5.0 5.5 v so, fs tri-state capacitance (15) c so ? ? 20 pf input logic pulldown resistor ( rst ) and wake r dwn 100 200 400 k ? input capacitance (15) c in ? 4.0 12 pf wake input clamp voltage (16) i cl(wake) < 2.5 ma v cl(wake) 7.0 ? 14 v wake input forward voltage i cl(wake) = -2.5 ma v f(wake) - 2.0 ? - 0.3 v so high-state output voltage i oh = 1.0 ma v soh 0.8 v dd ? ? v fs , so low-state output voltage i ol = -1.6 ma v sol ? 0.2 0.4 v so tri-state leakage current cs >=0.7vdd, 0 analog integrated circuit device data freescale semiconductor 9 33580 electrical characteristics static electical characteristics control interface (sclk, si, so, in[0:3], rst , wake, fs , cs , fsi) (continued) fsi input pin external pulldown resistance (18) fsi disabled, hs[0:3] state according to direct inputs state and spi inx_spi bits and a/o_s bit fsi enabled, hs[0:3] off fsi enabled, hs0 on, hs[1:3] off fsi enabled, hs0 and hs2 on, hs1 and hs3 off rfs ? 6.0 15 40 0 6.5 17 infinite 1.0 7.0 19 ? kohms temperature feedback t a = 25 c t feed 3.8 3.9 4.0 v temperature feedback derating dt feed -7.2 -7.5 -7.8 mv/c notes 18. the selection of the rfs must take into consideration the tolerance, temperature coefficient and lifetime duration to assure that the resistance value will always be wi thin the desired (specified) range. table 3. static electrical characteristics (continued) characteristics noted under conditions 6.0 v v pwr 27 v, 4.5 v v dd 5.5 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted refl ect the approximate par ameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit analog integrated circuit device data 10 freescale semiconductor 33580 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 6.0 v v pwr 27 v, 4.5 v v dd 5.5 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted refl ect the approximate par ameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power output timing (hs0, hs1, hs2, hs3) output rising slow slew rate a (dicr d3 = 0) (19) 9.0 v < v pwr < 16 v sr ra_slow 0.2 0.6 1.5 v/ s output rising slow slew rate b (dicr d3 = 0) (20) 9.0 v < v pwr < 16 v sr rb_slow 0.025 0.1 0.225 v/ s output rising fast slew rate a (dicr d3 = 1) (19) 9.0 v < v pwr < 16 v sr ra_fast 0.06 0.2 4.0 v/ s output rising fast slew rate b (dicr d3 = 1) (20) 9.0 v < v pwr < 16 v sr rb_fast 0.025 0.3 1.1 v/ s output falling slow slew rate a (dicr d3 = 0) (19) 9.0 v < v pwr < 16 v sr fa_slow 0.2 0.6 1.5 v/ s output falling slow slew rate b (dicr d3 = 0) (20) 9.0 v < v pwr < 16 v sr fb_slow 0.025 0.1 0.225 v/ s output falling fast slew rate a (dicr d3 = 1) (19) 9.0 v < v pwr < 16 v sr fa_fast 1.2 3.5 5.0 v/ s output falling fast slew rate b (dicr d3 = 1) (20) 9.0 v < v pwr < 16 v sr fb_fast 0.025 0.7 1.1 v/ s direct input switching frequency (dicr d3 = 0) f pwm - 300 - hz notes 19. rise and fall slew rates a measured across a 5.0 ? resistive load at high-side output = 0.5 v to v pwr - 3.5 v (see figure 4 , page 13 ). these parameters are guaranteed by process monitoring. 20. rise and fall slew rates b measured across a 5.0 ? resistive load at high-side output = 0.5 v to v pwr - 3.5 v (see figure 4 ). these parameters are guaranteed by process monitoring. analog integrated circuit device data freescale semiconductor 11 33580 electrical characteristics dynamic electrical characteristics power output timing (hs0, hs1, hs2, hs3) (continued) output turn-on delay time in slow slew rate (21) dicr = 0 t dly_slow(on) 2.0 10 130 s output turn-on delay time in fast slew rate (21) dicr = 1 t dly_fast(on) 1.0 3.0 60 s output turn-off delay time in slow slew rate mode (22) dicr = 0 t dly_slow(off) 20 100 400 s output turn-off delay time in fast slew rate mode (22) dicr = 1 t dly_fast(off) 5.0 20 100 s overcurrent low detection blanking time oclt[1:0] : 00 oclt[1:0] : 01 (23) oclt[1:0] : 10 oclt[1:0] : 11 t ocl0 t ocl1 t ocl2 t ocl3 108 ? 55 0.08 155 ? 75 0.15 202 ? 95 0.3 ms overcurrent high detection blanking time t och 1.0 5 20 s cs to csns valid time (24) t cnsval ? ? 10 s watchdog timeout (25) wd[1:0] : 00 wd[1:0] : 01 wd[1:0] : 10 wd[1:0] : 11 t wdto0 t wdto1 t wdto2 t wdto3 446 223 1800 900 558 279 2250 1125 725 363 2925 1463 ms notes 21. turn-on delay time measured from rising edge of any signal (in[0 : 3], sclk, cs ) that would turn the output on to v hs[0 : 3] = 0.5 v with r l = 5.0 ? resistive load. 22. turn-off delay time measured from falling edge of any signal (in[0 : 3], sclk, cs ) that would turn the output off to v hs[0 : 3] = v pwr - 0.5 v with r l = 5.0 ? resistive load. 23. this logical bit is not defined. do not use. 24. time necessary for the csns to be with 5% of the targeted value. 25. watchdog timeout delay measured from the rising edge of wake or rst from a sleep state condition, to output turn-on with the output driven off and fsi floating. the values shown are for wdr setting of [00]. the accuracy of t wdto is consistent for all configured watchdog time-outs. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v v pwr 27 v, 4.5 v v dd 5.5 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted refl ect the approximate par ameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit analog integrated circuit device data 12 freescale semiconductor 33580 electrical characteristics dynamic electrical characteristics spi interface characteristics maximum frequency of spi operation f spi ? ? 3.0 mhz required low state duration for rst (26) t wrst ? 50 350 ns rising edge of cs to falling edge of cs (required setup time) (27) t cs ? ? 300 ns rising edge of rst to falling edge of cs (required setup time) (27) t enbl ? ? 5.0 s falling edge of cs to rising edge of sclk (required setup time) (27) t lead ? 50 167 ns required high state duration of sclk (required setup time) (27) t wsclkh ? ? 167 ns required low state duration of sclk (required setup time) (27) t wsclkl ? ? 167 ns falling edge of sclk to rising edge of cs (required setup time) (27) t lag ? 50 167 ns si to falling edge of sclk (required setup time) (28) t si (su) ? 25 83 ns falling edge of sclk to si (required setup time) (28) t si (hold) ? 25 83 ns so rise time c l = 200 pf t rso ? 25 50 ns so fall time c l = 200 pf t fso ? 25 50 ns si, cs , sclk, incoming signal rise time (28) t rsi ? ? 50 ns si, cs , sclk, incoming signal fall time (28) t fsi ? ? 50 ns time from falling edge of cs to so low impedance (29) t so(en) ? ? 145 ns time from rising edge of cs to so high impedance (30) t so(dis) ? 65 145 ns time from rising edge of sclk to so data valid (31) 0.2 v dd so 0.8 v dd , c l = 200 pf t valid ? 65 105 ns notes 26. rst low duration measured with outputs enabl ed and going to off or disabled condition. 27. maximum setup time required for the 33580 is the mi nimum guaranteed time needed from the microcontroller. 28. rise and fall time of incoming si, cs , and sclk signals suggested for des ign consideration to prevent the occurrence of double pulsing. 29. time required for output status data to be available for use at so. 1.0 k ? on pullup on cs . 30. time required for output status data to be terminated at so. 1.0 k ? on pullup on cs . 31. time required to obtain valid data out from so following the rise of sclk. table 4. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v v pwr 27 v, 4.5 v v dd 5.5 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted refl ect the approximate par ameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit analog integrated circuit device data freescale semiconductor 13 33580 electrical characteristics timing diagrams timing diagrams figure 4. output slew rate and time delays figure 5. overcurrent shutdown t vpwr vpwr - 0.5v vpwr - 3v 0.5v v pwr pwr -0.5 v pwr -3.5 v 0.5 v t dly_slow(off) & t dly_fast(off) sr rb_slow & sr rb sr fb_slow & sr fb_fast sr fa_slow & sr fa_fast sr ra_slow & sr ra_fast cs t dly(on) v v load current i ochx i oclx t oclx time t och analog integrated circuit device data 14 freescale semiconductor 33580 electrical characteristics timing diagrams figure 6. overcurrent low and high detection figure 7. input timing switching characteristics i och 0 t ocl0 t ocl2 t ocl3 t och time load current i och1 i ocl0 i ocl2 i ocl3 i ocl4 i ocl5 i ocl6 i ocl7 i ocl1 si rstb csb sclk don?t care don?t care don?t care valid valid vih vil vih vih vih vil vil vil twrstb tlead twsclkh trsi tlag tsisu twsclkl tsi(hold) tfsi 0.7 vdd 0.2 vdd 0.7vdd 0.2vdd 0.2vdd 0.7vdd 0.7vdd tcsb tenbl rst sclk si cs 0.2 v dd t w rst t enbl 0.2 v dd t lead t wsclkh t rsi 0.7 v dd 0.2 v dd 0.7 v dd 0.2 v dd t si(su) t wsclkl t si(hold) t fsi 0.7 v dd t cs t lag v ih v ih v il v il v ih v il v ih v ih analog integrated circuit device data freescale semiconductor 15 33580 electrical characteristics timing diagrams figure 8. sclk waveform and valid so data delay time so so sclk voh vol voh vol voh vol tfsi tdlylh tdlyhl t valid trso tfso 3.5v 50% trsi high-to-low 1.0v 0.7 vdd 0.2vdd 0.2 vdd 0.7 vdd low-to-high t rsi t fsi 0.7 v dd sclk so so v oh v ol v oh v ol v oh v ol 1.0 v 0.2 v dd 0.7 v dd t rso t fso 0.2 v dd t so(en) t so(dis) 3.5 v low to high high to low t valid analog integrated circuit device data 16 freescale semiconductor 33580 functional description introduction functional description introduction the 33580 is one in a family of devices designed for low- voltage automotive and industrial lighting and motor control applications. its four low r ds(on) mosfets (15 m ? ) can control the high sides of four separate resistive or inductive loads. programming, control, and diagnostics are accomplished using a 16-bit spi interface. additionally, each output has its own parallel input for pwm control if desired. the 33580 allows the user to program via the spi the fault current trip levels and duration of acceptable lamp inrush or motor stall intervals. such prog rammability allows tight control of fault currents and can protect wiring harnesses and circuit boards as well as loads. the 33580 is packaged in a power-enhanced 12 x 12 nonleaded pqfn package with exposed tabs. functional pin description output current monitoring (csns) the current sense pin sources a current proportional to the designated hs0 : hs3 output. that current is fed into a ground-referenced resistor and its voltage is monitored by an mcu's a/d. the output to be monitored is selected via the spi. this pin can be tri-stated through spi. serial inputs (in0, in1, in2, in3) the in0 : in3 high-side input pins are used to directly control hs0 : hs3 high-side output pins, respectively. an spi register determines if each input is activated or if the input logic state is or ed or and ed with the spi instruction. these pins are to be driven with 5.0 v cmos levels, and they have an active internal pulldown current source. temperature feedback (temp) this pin reports an analog volt age value proportional to the temperature of the g nd. it is used by the mcu to monitor board temperature. fault status ( fs ) this pin is an open drain configured output requiring an external pullup resistor to v dd for fault reporting. if a device fault condition is detected, this pin is active low. specific device diagnostic faults are reported via the spi so pin. wake (wake) this input pin controls the device mode and watchdog timeout feature if enabled. an in ternal clamp protects this pin from high damaging voltages when the output is current limited with an external resi stor. this input has a passive internal pulldown. reset ( rst ) this input pin is used to initialize the device configuration and fault registers, as well as place the device in a low- current sleep mode. the pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. this pin should not be allowed to be logic [1] until v dd is in regulation. this pin has a passive internal pulldown. chip select ( cs ) the cs pin enables communicat ion with the master microcontroller (mcu). when this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the mcu. the 33580 latches in data from the input shift regi sters to the addressed registers on the rising edge of cs . the device transfers status information from the power outpu t to the shift register on the falling edge of cs . the so output driver is enabled when cs is logic [0]. cs should transition from a logic [1] to a logic [0] state only when sclk is a logic [0]. cs has an active internal pullup, i up . serial clock (sclk) the sclk pin clocks the internal shift registers of the 33580 device. the serial input (si) pin accepts data into the input shift register on the fa lling edge of the sclk signal while the serial output (so) pin shifts data information out of the so line driver on the rising edge of the sclk signal. it is important the sclk pin be in a logic low state whenever cs makes any transition. for this reason, it is recommended the sclk pin be in a logic [0] whenever the device is not accessed ( cs logic [1] state). sclk has an active internal pulldown. when cs is logic [1], signals at the sclk and si pins are ignored and so is tri-stated (high impedance) (see figure 9 , page 18 ). serial input (si) this is a serial interface (si) command data input pin. each si bit is read on the falling edge of sclk. a 16-bit stream of serial data is required on the si pin, starting with d15 to d0. the internal registers of the 33580 are configured and controlled using a 5-bit addressing scheme described in table 8 , page 22 . register addressing and configuration are described in table 9 , page 22 . the si input has an active internal pulldown, i dwn . digital drain voltage (vdd) this pin is an external voltage input pin used to supply power to the spi circuit. in the event v dd is lost, an internal analog integrated circuit device data freescale semiconductor 17 33580 functional description functional pin description supply provides power to a portion of the logic, ensuring limited functionality of the device. ground (gnd) this pin is the ground for the device. positive power supply (vpwr) this pin connects to the positive power supply and is the source of operational power for the device. the v pwr contact is the backside surface mount tab of the package. serial output (so) the so data pin is a tri-stateable output from the shift register. the so pin remains in a high-impedance state until the cs pin is put into a logic [0] state. the so data is capable of reporting the status of the ou tput, the device configuration, and the state of the key inputs. the so pin changes state on the rising edge of sclk and reads out on the falling edge of sclk. fault and input status descriptions are provided in table 16 , page 26 . high-side outputs (hs3, hs1, hs0, hs2) protected 15 m ? high-side power output pins to the load. fail-safe input (fsi) the value of the resistance connected between this pin and ground determines the state of the outputs after a watchdog timeout occurs. depending on the resistance value, either all outputs are off or the output hso only is on. if the fsi pin is left to float up to a logic [1] level, then the outputs hs0 and hs2 will turn on when in the fail-safe state. when the fsi pin is c onnected to gnd, the watchdog circuit and fail-safe operation are disabled. this pin incorporates an active internal pullup current source. analog integrated circuit device data 18 freescale semiconductor 33580 functional device operation operational modes functional device operation spi protocol description the spi interface has a full duplex, three-wire synchronous data transfer with four i/o lines associated with it: serial input (si), serial ou tput (so), serial clock (sclk), and chip select ( cs ). the si / so pins of the 33580 follow a first-in first-out (d15 to d0) protocol, with both input and output words transferring the most significant bit (msb) first. all inputs are compatible with 5.0 v cmos logic levels. figure 9. single 16-bit word spi communication operational modes the 33580 has four operating modes: sleep, normal, fault, and fail-safe. table 5 summarizes details contained in succeeding paragraphs. sleep mode the default mode of the 33580 is the sleep mode. this is the state of the device after first applying battery voltage (v pwr ) prior to any i/o transitions. this is also the state of the device when the wake and rst are both logic [0]. in the sleep mode, the output and all u nused internal circuitry, such as the internal 5.0 v regulator, are off to minimize current draw. in addition, all spi-configurable features of the device are as if set to logic [0]. the 33580 will transition to the normal or fail-safe operating modes based on the wake and rst inputs as defined in table 5 . normal mode the 33580 is in normal mode when: ?v pwr and v dd are within the normal voltage range. ? rst pin is logic [1]. ? no fault has occurred. fail-safe mode fail-safe mode and watchdog if the fsi input is not grounded, the watchdog timeout detection is active wh en either the wake or rst input pin transitions from logic [0] to logic [1]. the wake input is capable of being pulled up to v pwr with a series of limiting cs csb si sclk so d15 d1 d2 d3 d4 d5 d6 d7 d8 d9 d14 d13 d12 d11 d10 od12 d0 od13 od14 od15 od6 od7 od8 od9 od10 od11 od1 od2 od3 od4 od5 1. rstb is in a logic h state during the above operation. 2. do, d1, d2, ... , and d15 relate to the most recent ordered entry of program data into the lux ic notes: od0 cs device. 1. rst is a logic [1] state during the above operation. 2. d15 : d0 relate to the most recent ordered entry of data into the device. 3. od15 : od0 relate to the first 16 bits of ordered fault and status data out of the device. notes table 5. fail-safe operation and transitions to other 33580 modes mode fs wake rst wdto comments sleep x 0 0 x device is in sleep mode. all outputs are off normal 1 x 1 no normal mode. watchdog is active if enabled. fault 0 1 1 no device is currently in fault mode. the faulted output(s) is (are) off. 0 1 0 0 0 1 fail- safe 1 0 1 yes watchdog has timed out and the device is in fail-safe mode. the outputs are as configured with the rfs resistor connected to fsi. rst and wake must go from logic [1] to logic [0] simultaneously to bring the device out of the fail-safe mode or momentarily tied the fsi pin to ground. 1 1 1 1 1 0 x = don?t care. analog integrated circuit device data freescale semiconductor 19 33580 functional device operation protection and di agnostic features resistance limiting the internal clamp current according to the specification. the watchdog timeout is a multip le of an internal oscillator and is specified in the table 15 , page 24 . as long as the wd bit (d15) of an incoming spi message is toggled within the minimum watchdog timeout period (wdto), based on the programmed value of the wdr, the device will operate normally. if an internal watchdog timeout occurs before the wd bit, the device will revert to a fail-safe mode until the device is reinitialized. during the fail-safe mode, the outputs will be on or off depending upon the resistor rfs connected to the fsi pin, regardless of the state of the various direct inputs and modes ( table 6 ) . in the fail-safe mode, the spi register content is retained except for overcurrent high and low detection levels, timing and latched overtemperature which are reset to their default value (socl, soch, octl and ot_latch_[0:3] bits ). then the watchdog, overvoltage, overte mperature, and overcurrent circuitry (with default value) are fully operational. the fail-safe mode can be detected by monitoring the wdto bit d2 of the wd register. this bit is logi c [1] when the device is in fail-safe mode. the device can be brought out of the fail-safe mode by tr ansitioning the wake and rst pins from logic [1] to logic [0] or forcing the fsi pin to logic [0]. table 5 summarizes the various methods for resetting the device from the latched fail-safe mode. if the fsi pin is tied to gnd, the watchdog fail-safe operation is disabled. loss of v dd if the external 5.0 v supply is not within specification, or even disconnected, all register content is reset. the outputs can still be driven by the direct inputs in0 : in3. the 33580 uses the battery input to power the output mosfet-related current sense circuitry and any other internal logic providing fail-safe device operation with no v dd supplied. in this state, the watchdog, undervoltage, ov ervoltage, overtemperature (latched), and overcurrent circ uitry are fully operational with default values. fault mode this 33580 indicates the faults below as they occur by driving the fs pin to logic [0]: ? overtemperature fault ? overvoltage and undervoltage fault ? open load fault ? overcurrent fault (high and low) the fs pin will automatically return to logic [1] when the fault condition is removed, except for overcurrent, overtemperature (in case of la tching configuration) and in some cases of undervoltage. the fs pin reports all faults. for latched faults, this pin is reset by a new switch on command (via spi or direct input in). fault information is retained in the fault register and is available (and reset) via the so pin during the first valid spi communication (refer to table 17 , page 26 ). protection and diagnostic features overtemperature fault (latching or non-latching) the 33580 incorporates over temperature detection and shutdown circuitry for each output structure. the overtemperature is la tched per default and can be unlatched through spi with ot_latch_[0:3] bits. an overtemperature fault cond ition results in turning off the corresponding output. to remove the fault and be able to turn on again the outputs, the failure must be removed and: ? in normal mode: the corresponding output must be commanded off and on again in case of overtemperature latched ( ot_latch bit = 0) . ? in normal mode: the corresponding output turns on automatically if the temperature is below t sd -t sd(hys) in case of unlatched overtemperature ( ot_latch bit = 1). ? in fail-safe mode: the fsi input must be grounded and then set to its nominal voltage to switch on the outputs. the overtemperature fault (one for each output) is reported by spi. if the overte mperature is latched, the spi reports otf_s = [1] and oclf_s = [1]. in case of non- latched, otf_s = [1] only is reported. the fault bits will be cleared in the status register after either a valid spi read command or a power on reset of the device. table 6. output state during fail-safe mode rfs (k ? ) high-side state 0 (shorted to ground) fail-safe mode disabled 6.0 all hs off 15 hs0 on hs1 : hs3 off 30 (open) hs0 and hs2 on hs1 and hs3 off analog integrated circuit device data 20 freescale semiconductor 33580 functional device operation protection and di agnostic features overcurrent fault (latching) the 33580 has eight programmable overcurrent low detection levels (i ocl ) and two programmable overcurrent high detection levels (i och ) for maximum device protection. the two selectable, simultaneously active overcurrent detection levels, defined by i och and i ocl , are illustrated in figure 6 , page 14 . the eight different overcurrent low detect levels (i ocl0 : i ocl7 ) are illustrated in figure 6 . if the load current level ever reaches the selected overcurrent low detection level and the overcurrent condition exceeds the programmed overcurrent time period (t oc x ), the device will latch the output off. if at any time the curren t reaches the selected i och level, then the device will immediately latch the fault and turn off the output, regardless of the selected t och driver. for both cases, the device output will stay off indefinitely until the device is commanded off and then on again. overvoltage fault (non-latching) the 33580 shuts down the out put during an overvoltage fault (ovf) condition on the v pwr pin. the output remains in the off state until the overvo ltage condition is removed. when experiencing this fault, the ovf fault bit is set in the bit d1 and cleared after either a valid spi read or a power reset of the device. the overvoltage protection c an be disabled through spi (bit ov_dis). when disabled, the returned so bit od13 still reflects any overvoltage condition (overvoltage warning). undervoltage shutdown (latching or non-latching) the output(s) will latch off at some battery voltage below 6.0 v. as long as the v dd level stays within the normal specified range, the internal logic states within the device will be sustained. in the case where battery voltage drops below the undervoltage threshold (vpwruv) output will turn off, fs will go to logic 0, and the fault re gister uvf bit will be set to 1. two cases need to be considered when the battery level recovers : ? if outputs command are low, fs will go to logic 1 but the uvf bit will remain set to 1 until the next read operation (warning report). ? if the output command is on, then fs will remain at logic 0. the output must be turned off and on again to re-enable the state of output and release fs . the uvf bit will remain set to 1 until the next read operation. the undervoltage protection can be disabled through spi (bit uv_dis = 1). in this case, the fs does not report any undervoltage fault condition, uvf bit is set to 1, and the output state is not changed as long as the battery voltage does not drop any lower than 2.5 v. in case of v pwr is missing, the daisy chain feature is available under v dd in nominal conditions. analog integrated circuit device data freescale semiconductor 21 33580 functional device operation protection and di agnostic features open load fault (non-latching) the 33580 incorporates open load detection circuitry on the output. output open load fault (olf) is detected and reported as a fault condition when the output is disabled (off). the open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn off the output. t he olf fault bit is set in the status register. if the open load fault is removed, the status register will be cleared after reading the register. the open load protection can be disabled through spi (bit ol_dis). it is recommended to disable the open load detection circuitry in case of permanent disconnected load. reverse battery the output survives the applic ation of reverse voltage as low as -16 v. under these cond itions, the output?s gate is enhanced to keep the junction temperature less than 150c. the on resistance of the output is fairly similar to that in the normal mode. no additional passive components are required except on v dd . ground disconnect protection in the event the 33580 ground is disconnected from load ground, the device protects itself and safely turns off the output regardless of the state of the output at the time of disconnection. a 10k resistor needs to be added between the wake pin and the rest of the circ uitry in order to ensure that the device turns off in case of ground disconnect and to prevent this pin to exce ed its maximum ratings. current limit resistors in the digital input lines protect the digital supply against excessive current (1 kohm typical). table 7. device behavior in case of undervoltage quad high-side switch (vpwr battery voltage) ?? state uv enable in[0:3]=0 (falling vpwr) uv enable in[0:3]=0 (falling or rising vpwr) uv enable in_x***=1 (falling vpwr) uv enable in_x***=1 (rising vpwr) uv disable in[0:3]=0 (falling or rising vpwr) uv disable in_x***=1 (falling or rising vpwr) vpwr > vpwruv output state off off on off off on fs state 1 1 1 0 1 1 spi fault register uvf bit 0 1 until next read 0 1 0 (falling) 1 until next read (rising) 0 (falling) 1 until next read (rising) vpwruv > vpwr > uvpor output state off off off off off on fs state 0 0 0 0 1 1 spi fault register uvf bit 1 1 1 1 1 1 uvpor > vpwr > 2.5 v ? output state off off off off off on fs state 1 1 1 1 1 1 spi fault register uvf bit 1 until next read 1 1 until next read 1 until next read 1 until next read 1 until next read 2.5 v > vpwr > 0v output state off off off off off off fs state 1 1 1 1 1 1 spi fault register uvf bit 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read comments uv fault is not latched uv fault is not latched uv fault is latched ? = typical value; not guaranteed. ?? = while v dd remains within specified range. ??? = in_x is equivalent to in_x di rect input or in_spi_s spi input. analog integrated circuit device data 22 freescale semiconductor 33580 functional device operation logic commands and registers logic commands and registers serial input communication spi communication is accomplished using 16-bit messages. a message is transm itted by the mcu starting with the msb d15 and ending with the lsb, d0 ( table 8 ). each incoming command message on the si pin can be interpreted using the following bit assignments: the msb, d15, is the watchdog bit. in some cases, outpu t selection is done with bits d12 : d11. the next three bits, d10 : d8, are used to select the command register. the remaining five bits, d4 : d0, are used to configur e and control the outputs and their protection features. multiple messages can be transmitted in succession to accommodate those applications where daisy-chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16 bits. any attempt made to latch in a message that is not 16 bits will be ignored. the 33580 has defined register s, which are used to configure the device and to cont rol the state of the outputs. table 9 , page 22 , summarizes the si registers. table 8. si message bit assignment bit sig si msg bit message bit description msb d15 watchdog in: toggled to satisfy watchdog requirements. d14 : d15 not used. d12 : d11 register address bits used in some cases for output selection. d10 : d8 register address bits. d7 : d5 not used. d4 : d1 used to configure the inputs, outputs, and the devi ce protection features and so status content. lsb d0 used to configure the inputs, outputs, and the devi ce protection features and so status content. table 9. serial input address and configuration bit map si register si data d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 statr_s wdin 0 0 0 0 0 0 0 0 0 0 soa4 soa3 soa2 soa1 soa0 ocr0 wdin 0 0 0 0 0 0 1 0 0 0 0 in3_spi in2_spi in1_spi in0_spi ocr1 wdin 0 0 0 1 0 0 1 0 0 0 0 csns3 en csns2 en csns1 en csns0 en sochlr_s wdin 0 0 a 1 a 0 0 1 0 0 0 0 0 soch_s socl2_s socl1_s socl0_s cdtolr_s wdin 0 0 a 1 a 0 0 1 1 0 0 0 0 ol_dis_s ocl_dis_s oclt1_s oclt0_s dicr_s wdin 0 0 a 1 a 0 1 0 0 0 0 0 0 fast_sr_s csns_high_s dir_dis_s a/o_s uovr wdin 0 0 0 0 1 0 1 0 0 0 0 ot_latch-1 ot_latch_0 uv_dis ov_dis wdr wdin 0 0 0 1 1 0 1 0 0 0 0 ot_latch_3 ot_latch_2 wd1 wd0 nar wdin 0 0 0 0 1 1 0 0 0 0 0 no action (allow toggling of d15 - wdin) reset 0 0 0 x x x x x 0 0 0 0 0 0 0 0 x = don?t care. s = output selection with the bits a 1 a 0 as defined in table 10 . d15 is used to toggle watchdog event (wdin). analog integrated circuit device data freescale semiconductor 23 33580 functional device operation logic commands and registers device register addressing the following section describes the possible register addresses and their impact on device operation. address 00000 ? status register (statr_s) the statr register is used to read the device status and the various configuration register contents without disrupting the device operation or the regist er contents. the register bits d[4:0] determine the content of the first sixteen bits of so data. in addition to the device st atus, this feature provides the ability to read the content of the ocr0, ocr1, sochlr, cdtolr, dicr, uovr, wdr, and nar registers. (refer to the section entitled serial output communication (device status return data) beginning on page 25 .) address 00001? output control register (ocr0 ) the ocr0 register allows the mcu to control the on / off state of four outputs through the spi. incoming message bit d3 : d0 reflects the desired states of the four high-side outputs (inx_spi), respective ly. a logic [1] enables the corresponding output switch and a logic [0] turns it off. address 01001? output control register (ocr1 ) incoming message bits d3 : d0 reflect the desired output that will be mirrored on the current sense (csns) pin. a logic [1] on message bits d3 : d0 enables the csns pin for outputs hs3 : hs0, respective ly. in the event the current sense is enabled for multiple outputs, the current will be summed. in the event that bits d3 : d0 are all logic [0], the output csns will be tr i-stated. this is useful when several csns pins of several devices share the same a /d converter. address a 1 a 0 010 ? select overcurrent high and low register (sochlr_s) the sochlr_s register allows the mcu to configure the output overcurrent low and high detection levels, respectively. each output ?s? is independently selected for configuration based on the st ate of the d12 : d11 bits ( table 10 ). each output can be configured to different levels. in addition to protecting the device, this slow blow fuse emulation feature can be us ed to optimize the load requirements matching system characteristics. bits d2 : d0 set the overcurrent low detection level to one of eight possible levels, as shown in table 11 , page 23 . bit d3 sets the overcurrent high detection level to one of two levels, as outlined in table 12 , page 23 . address a 1 a 0 011 ? current detection time and open load register (cdtolr) the cdtolr register is used by the mcu to determine the amount of time the device will allow an overcurrent low condition before an output la tches off. each output is independently selected for configuration based on a 1 a 0 , which are the state of the d12 : d11 bits (refer to table 10 , page 23 ). table 10. output selection a 1 (d12) a 0 (d11) hs_s 0 0 hs0 0 1 hs1 1 0 hs2 1 1 hs3 table 11. overcurrent low detection levels socl2_s * (d2) socl1_s * (d1) socl0_s * (d0) overcurrent low detection (amperes) hs0 to hs3 0 0 0 18.2 0 0 1 16.3 0 1 0 14.4 0 1 1 12.5 1 0 0 10.5 1 0 1 8.6 1 1 0 6.7 1 1 1 4.8 * ?_s? refers to the output, which is selected through bits d12 : d11; refer to table 10 , page 23 . table 12. overcurrent high detection levels soch_s * (d3) overcurrent high detection (amperes) hs0 to hs3 0 100 1 70 * ?_s? refers to the output, which is selected through bits d12 : d11; refer to table 10 , page 23 . analog integrated circuit device data 24 freescale semiconductor 33580 functional device operation logic commands and registers bits d1 : d0 (oclt1_s : oclt0_s) allow the mcu to select one of three overcurrent fault blanking times defined in table 13 . note that these time-outs apply only to the overcurrent low detection levels. if the selected overcurrent high level is reached, the device will latch off within 20 s . a logic [1] on bit d2 (ocl_dis_s) disables the overcurrent low detection feature. when disabled, there is no timeout for the selected output and the over current low detection feature is disabled. a logic [1] on bit d3 (ol_dis_s) disables the open load (ol) detection feature for the output corresponding to the state of bits d12 : d11. address a 1 a 0 100 ? direct input control register (dicr) the dicr register is used by the mcu to enable, disable, or configure the direct in pi n control of each output. each output is independently selected for configuration based on the state bits d12 : d11 (refer to table 10 , page 23 ). for the selected output, a logic [0] on bit d1 (dir_dis_s) will enable the output for direct control. a logic [1] on bit d1 will disable the output from direct control. while addressing this register, if the input was enabled for direct control, a logic [1] for t he d0 (a/o_s) bit will result in a boolean and of the in pin with its corresponding in_spi d[4:0] message bit when addre ssing ocr0. similarly, a logic [0] on the d0 pin results in a boolean or of the in pin to the corresponding message bits when addressing the ocr0. this register is especially usef ul if several loads are required to be independently pwm contro lled. for example, the in pins of several devices can be configured to operate all of the outputs with one pwm output fr om the mcu. if each output is then configured to be boolean anded to its respective in pin, each output can be individually turned off by spi while controlling all of the outputs, commanded on with the single pwm output. a logic [1] on bit d2 (csns_high_s) is used to select the high ratio on the csns pin for the selected output. the default value [0] is used to select the low ratio ( table 14 ). a logic [1] on bit d3 (fast_sr_ s) is used to select the high speed slew rate for the selected output, the default value [0] corresponds to the low speed slew rate. address 00101 ? undervoltage / overvoltage and hs[0,1] overtemperature register (uovr) the uovr register disables the undervoltage (d1) and/or overvoltage (d0) protection. w hen these two bits are [0], the under- and overvoltage are active (default value). the uovr register allows the overtemperature detection latching on the hs0 and hs1. to latch the overtemperature, the bits (ot_latch_1 and ot_latch_0 ) must be set to [0] which is the default value. to disable the latching, both bits must be set to [1]. address 01101 ? watchdog and hs[2,3] overtemperature register (wdr) the wdr register is used by the mcu to configure the watchdog timeout. the watch dog timeout is configured using bits d1 and d0. when d1 and d0 bits are programmed for the desired watchdog timeout period ( table 15 ), the wdspi bit should be toggled as well, ensuring the new timeout period is programmed at the beginning of a new count sequence. the wdr register allows the overtemperature detection latching on the hs2 and hs3. to latch the overtemperature, the bits (ot_latch_3 and ot_latch_2 ) must be set to [0] which is the default value. to disable the latching, both bits must be set to [1]. table 13. overcurrent lo w detection blanking time oclt[1:0]_s * timing 00 155 ms 01 do not use 10 75 ms 11 150 s * ?_s? refers to the output, which is selected through bits d12 : d11. table 14. current sense ratio csns_high_s * (d2) current sense ratio hs0 to hs3 0 1/13000 1 1/38000 * ?_s? refers to the output, which is selected through bits d12 : d11; refer to table 10 , page 23 . table 15. watchdog timeout wd[1:0] (d1, d0) timing (ms) 00 558 01 279 10 2250 11 1125 analog integrated circuit device data freescale semiconductor 25 33580 functional device operation logic commands and registers address 00110 ? no action register (nar) the nar register can be used to no-operation fill spi data packets in a daisy-chain spi co nfiguration. this would allow devices to be unaffected by commands being clocked over a daisy-chained spi configurati on. by toggling the wd bit (d15) the watchdog circuitry would continue to be reset while no programming or data read back functions are being requested from the device. serial output communication (device status return data) when the cs pin is pulled low, the output register is loaded. meanwhile, the data is clocked out msb- (od15-) first as the new message data is clocked into the si pin. the first sixteen bits of data clocking out of the so, and following a cs transition, is dependent upon the previously written spi word. any bits clocked out of the serial output (so) pin after the first 16 bits will be representative of the initial message bits clocked into the si pin since the cs pin first transitioned to a logic [0]. this feature is useful for daisy-chaining devices as well as message verification. a valid message length is determined following a cs transition of [0] to [1]. if there is a valid message length, the data is latched into the appr opriate registers. a valid message length is a multiple of 16 bits. at this time, the so pin is tri-stated and the fault st atus register is now able to accept new fault status information. so data will represent information ranging from fault status to register contents, us er selected by writing to the statr bits od4, od3, od2, od1, and od0. the value of the previous bits soa4 and soa3 will determine which output the so information applies to for the registers which are output specific; viz., fault, sochlr, cdtolr, and dicr registers. note that the so data will continue to reflect the information for each output (depending on the previous od4, od3 state) that was selected during the most recent statr write until changed with an updated statr write. the output status register corre ctly reflects the status of the statr-selected register data at the time that the cs is pulled to a logic [0] during spi communication, and/or for the period of time since the last valid spi communication, with the following exceptions: ? the previous spi communication was determined to be invalid. in this case, the status will be reported as though the invalid spi communication never occurred. ? battery transients below 6.0 v resulting in an under- voltage shutdown of the output s may result in incorrect data loaded into the status register. the so data transmitted to the mcu during the first spi communication following an undervoltage v pwr condition should be ignored. ? the rst pin transition from a logic [0] to [1] while the wake pin is at logic [0] may result in incorrect data loaded into the status regist er. the so data transmitted to the mcu during the first spi communication following this condition should be ignored. serial output bit assignment the 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. table 16 , page 26 , summarizes so returned data for bits od15 : od0. ? bit od15 is the msb; it reflects the state of the watchdog bit from the previously clocked-in message. ? bit od14 remains logic [0] except when an undervoltage condition occurred. ? bit od13 remains logic [0] except when an overvoltage condition occurred. ?bits od12 : od8 reflect the state of the bits soa4 : soa0 from the previously clocked in message. ? bits od7 : od4 give the fault stat us flag of the outputs hs3 : hs0, respectively. ? the contents of bits od3 : od0 depend on bits d4 : d0 from the most recent statr command soa4 : soa0 as explained in the paragraphs following table 16 . analog integrated circuit device data 26 freescale semiconductor 33580 functional device operation logic commands and registers previous address soa4 : soa0 = a 1 a 0 000 bits od3 : od0 reflect the current state of the fault register (fltr) corresponding to the output previously selected with the bits a 1 a 0 ( table 17 ). note the fs pin reports all faults. for latched faults, this pin is reset by a new switch off command (via spi or direct input in). previous address soa4 : soa0 = 00001 data in bits od3 : od0 contains in3_spi : in0_spi programmed bits for outputs hs3 : hs0, respectively. previous address soa4 : soa0 = 01001 data in bits od3 : od0 contains the programmed csns3 en : csns0 en bits for outputs hs3 : hs0, respectively. previous address soa4 : soa0 = a 1 a 0 010 data returned in bits od3 : od0 are programmed current values for the overcurrent high detection level (refer to table 12 , page 23 ) and the overcurrent low detection level (refer to table 11 , page 23 ), corresponding to the output previously selected with a 1 a 0 . previous address soa4 : soa0= a 1 a 0 011 the returned data contains the programmed values in the cdtolr register for the output selected with a 1 a 0 . previous address soa4 : soa0 = a 1 a 0 100 the returned data contains the programmed values in the dicr register for the ou tput selected with a 1 a 0 . previous address soa4 : soa0 = 00101 the returned data contains the programmed values in the uovr register. previous address soa4 : soa0 = 01101 the returned data contains the programmed values in the wdr register. bit od2 (wdto) reflects the status of the watchdog circuitry. if wdto bit is logic [1], the watchdog has timed out and the device is in fail-safe mode. if wdto is a logic [0], the device is in normal mode (assuming the device table 16. serial output bit map description previous statr so returned data so a4 so a3 so a2 so a1 so a0 od 15 od 14 od 13 od 12 od 11 od 10 od9 od8 od7 od6 od5 od4 od3 od2 od1 od0 statrs a 1 a 0 0 0 0 wdin uvf ovf soa4 soa3 soa2 soa1 soa0 st3 st2 st1 st0 otf_s ochf_s oclf_s olf_s ocr0 0 0 0 0 1 wdin uvf ovf soa4 soa3 soa2 soa1 soa0 st3 st2 st1 st0 in3_spi in2_spi in1_spi in0_spi ocr1 0 1 0 0 1 wdin uvf ovf soa4 soa3 soa2 soa1 soa0 st3 st2 st1 st0 csns3 en csns2 en csns1 en csns0 en sochl r_s a 1 a 0 0 1 0 wdin uvf ovf soa4 soa3 soa2 soa1 soa0 st3 st2 st1 st0 soch_s socl2_s socl1_s socl0_s cdtol r_s a 1 a 0 0 1 1 wdin uvf ovf soa4 soa3 soa2 soa1 soa0 st3 st2 st1 st0 ol_dis_s ocl_dis_s oclt1_s oclt0_s dicr_s a 1 a 0 1 0 0 wdin uvf ovf soa4 soa3 soa2 soa1 soa0 st3 st2 st1 st0 fast_sr_s csns_high_s dir_dis_s a/o_s uovr 0 0 1 0 1 wdin uvf ovf soa4 soa3 soa2 soa1 soa0 st3 st2 st1 st0 ot_latch_1 ot_latch_0 uv_dis ov_dis wdr 0 1 1 0 1 wdin uvf ovf soa4 soa3 soa2 soa1 soa0 st3 st2 st1 st0 0 wdto wd1 wd0 pinr0 0 0 1 1 0 wdin uvf ovf soa4 soa3 soa2 soa1 soa0 st3 st2 st1 st0 hs2_failsafe hs0_failsafe wd_en wake pinr1 0 1 1 1 0 wdin uvf ovf soa4 soa3 soa2 soa1 soa0 st3 st2 st1 st0 in3 in2 in1 in0 pinr2 0 1 1 1 1 wdin uvf ovf soa4 soa3 soa2 soa1 soa0 st3 st2 st1 st0 ot_latch_3 ot_latch_2 x x reset n/a n/a n/a n/a n/a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s = output selection with the bits a 1 a 0 as defined in table 10 , page 23 . table 17. output-specific fault register od3 od2 od1 od0 otf_s ochf_s oclf_s olf_s s = selection of the output. analog integrated circuit device data freescale semiconductor 27 33580 functional device operation logic commands and registers is powered and not in the sleep mode), with the watchdog either enabled or disabled. previous address soa4 : soa0 = 00110 the returned data od3 and od 2 contain the state of the outputs hs2 and hs0, respectively, in case of fail-safe state. this information is stated with the external resistance placed at the fsi pin. od1 indicates if the watchdog is enabled or not. od0 return s the state of the wake pin. previous address soa4 : soa0 = 01110 the returned data od3 : od0 reflects the state of the direct pins in3 : in0, respectively. previous address soa4 : soa0 = 01111 the returned data od3 -od2 reports the overtemperature bits configuration of the out puts [3, 2] set through the wdr spi register. analog integrated circuit device data 28 freescale semiconductor 33580 typical applications introduction typical applications introduction the 33580 can be configured in several applications. the figure below shows the 33580 in a typical lighting application. 33580 i/o v dd v dd v pwr gnd microcontroller voltage regulator v pwr 100nf hs2 hs0 hs1 hs3 vpwr vdd wake fs in0 in2 in3 sclk cs nc temp si so fsi rst in1 10f 100nf i/o i/o i/o i/o i/o sclk cs si so a/d 10k 10k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 1k r1 10 k load 0 load 1 load 2 load 3 csns a/d v dd v dd v pwr v dd automotive lamps do not tolerate high voltages very well. tests of a few lamps indicate that failures can occur when 18v is applied for a few seconds. consequently, pwm switching reduces the effective rms voltage in order to drive bulbs safety. for example, to maintain the power dissipation associated with a 13v ba ttery at 100% duty cycle, the duty cycle would be adjusted to (13/18)2, or 52%, when the bat tery is at 18v. the loads must be chosen in order to guarantee the device normal operating condition for junction tempera- ture from -40 to 150 c. in case of permanent short-ci rcuit conditions, the duration and number of activation cycles must be limited with a dedicated mcu fault man agement using the fault reporting through the spi. 55w 55w 55w 55w analog integrated circuit device data freescale semiconductor 29 33580 typical applications standalone mode standalone mode this section consists of evaluating the MC33580 standalone capability. configuration without mcu the standalone mode is intended for customers who desire to plug the device and then immediately ?play? with it, without having to connect it to a microcontroller. it also provides an easy way to evaluate the main electrical features. without the microcontroller to select programmable parameters and get full diagnosis via the spi, the MC33580 runs with all parameters set to default. the input spi pin pins and vdd must be connected to ground. fail safe mode a nd watchdog timeout must be disabled by connecting the fsi to gnd. all protection functions are available without spi communication. nevertheless, any configuration is possible without an mcu to communicate by spi. some functions still enable, but diagnosis is reduced. available functions and default parameters are detailed next. functioning without mcu without an mcu, spi communication is not possible. fail safe mode and watchdog timeout are not useful functions without an mcu, but still enab le. wake/sleep mode is used to minimize current consumption during sleep mode. in pins control the corresponding outputs and fs output is active (at 0 v) when a default occurs. table 18 illustrates the available functions without spi and default parameters. table 19 illustrates default parameters after resetting or applying supply voltage to the MC33580. levels and timings are typical values. table 18. available functions function with spi without spi wake/sleep mode available available output on/off control via spi or in pin only with in pin over temperature protection available, can be unlatched available over voltage protection available, can be disabled available, always enable under voltage protection available, can be disabled available, always enable over current protection available, configurable (with 8 low levels and 2 high levels), can be disabled available, always enable with default values open load, battery disconnect, reverse battery, ground disconnect protections available available fault diagnosis full diagnosis with re port by spi and fault status pin (/fs) limited fault diagnosis with fault status pin only current sense available, 2 configurable ratios not available watchdog timeout available, 4 configurable timings available, default value configurable slew rate 2 slew rate modes default slew rate mode analog temperature feedback available available table 19. default spi-conf igurable parameters configulable parameter default typical value over voltage protection enable under voltage protection enable over current protection enable over current low level oclo0 over current high level ochi0 over current detect blanking time t oclo0 current sense disable watchdog time timeout t wdto0 slew rate mode slow mode analog integrated circuit device data 30 freescale semiconductor 33580 typical applications standalone mode diagnosis without mcu when any fault appears (over current, open load?), a full diagnosis can be reported via the spi. without an mcu, the fault status pin allows reduced diagnosis, as illustrated in table 20 . we can note that it is not possible to distinguish over temperature, over current, under voltage , and over voltage. nevertheless, open load and short circuit to v pwr fault can be singled out. all protections ar e reported to fault status pin ( fs ), open load and short circuit to v pwr are reported only if the output is off. if the fault is latched, the output must be turned off then on to disable the fault. conclusion although the MC33580 is not fully functional without a microcontroller to control and program it, standalone functioning is safe because all protections are available. diagnosis is limited, but the fa ult status pin will report any malfunction. this is a good way to evaluate the main electrical MC33580 features. some simplified applications can also use the MC33580 switch without an mcu to drive a high power load with full protection. table 20. diagnosis without spi in[x] level hs[x] level fs level latched normal operation h h h n/a l l h over temperature l l l yes h l l under voltage l l l yes h l l over voltage l l h no h l l over current l l h yes h l l short circuit to vpwr l h l no h h h open load l z l no h h h h : high level, l : low level, z : high impedanc e, potential depends on the external circuit. analog integrated circuit device data freescale semiconductor 31 33580 packaging soldering information packaging soldering information the 33580 is not designed for immersion soldering. the maximu m peak temperature during the soldering process should not exceed 245 c. terminal soldering limit is for 10 seconds maximum duration. exceeding these limit s may cause malfunction or permanent damage to the device. package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the 98art10510d listed below. pna suffix (pb-free) 24-pin pqfn non-leaded package 98art10511d issue 0 analog integrated circuit device data 32 freescale semiconductor 33580 packaging package dimensions analog integrated circuit device data freescale semiconductor 33 33580 packaging package dimensions analog integrated circuit device data 34 freescale semiconductor 33580 additional documentation thermal addendum (rev 3.0) additional documentation thermal addendum (rev 3.0) introduction this thermal addendum is provided as a supplement to the MC33580 technical datasheet. the addendum pr ovides thermal performance information that may be critical in the design and development of system appl ications. all electrical, application, and packaging information is provided in the datasheet. packaging and thermal considerations this package is a dual die package. ther e are two heat sources in the package independently heating with p 1 and p 2 . this results in two junction temperatures, t j1 and t j2 , and a thermal resistance matrix with r ja mn . for m , n = 1, r ja11 is the thermal resistance from junction 1 to the reference temperature while only heat so urce 1 is heating with p 1 . for m = 1, n = 2, r ja12 is the thermal resistance from junction 1 to the reference temperature while heat source 2 is heating with p 2 . this applies to r j21 and r j22 , respectively. the stated values are solely for a thermal performance comparison of one package to another in a standard ized environment. this methodology is not meant to and will not predict the perfor mance of a package in an applic ation-specific environment. stat ed values were obtained by measurement and simula tion according to the standards listed below. high-side switch 33580pna pna suffix 98art10510d 24-pin pqfn (12 x 12) note for package dimensions, refer to the 33580 device datasheet. t j1 t j2 = r ja11 r ja21 r ja12 r ja22 . p 1 p 2 standards figure 10. surface mount for power pqfn with exposed pads table 21. thermal performance comparison thermal resistance 1 = power chip, 2 = logic chip [ c/w] m = 1, n = 1 m = 1, n = 2 m = 2, n = 1 m = 2, n = 2 r ja mn (1) , (2) 20 16 39 r jb mn (2) , (3) 62.026 r ja mn (1) , (4) 53 40 73 r jc mn (5) <0.5 0.0 1.0 notes: 1. per jedec jesd51-2 at natural convection, still air condition. 2. 2s2p thermal test board per jedec jesd51-7and jesd51-5. 3. per jedec jesd51-8, with the board temperature on the center trace near the power outputs. 4. single layer thermal test board per jedec jesd51-3 and jesd51-5. 5. thermal resistance between the die junction and the exposed pad, ?infinite? heat sink attached to exposed pad. note: recommended via diameter is 0.5 mm. pth (plated throug h hole) via must be plugged / filled with epoxy or solder mask in orde to minimize void formation and to avoid any solder wicking into th e via. 1.0 1.0 0.2 0.2 analog integrated circuit device data freescale semiconductor 35 33580 additional documentation thermal addendum (rev 3.0) figure 12. thermal test board device on thermal test board r ja is the thermal resistance between die junction and ambient air. this device is a dual die package. index m indicates the die that is heated. index n refers to the number of the die where the junction temperature is sensed. a = 300sqmm 76.2 mm 114.3 mm a = 300sqmm a = 300sqmm 76.2 mm 114.3 mm a = 300sqmm MC33580 pin connections 24-pin pqfn (12 x 12) 0.9 mm pitch 12.0 mm x 12.0 mm body 13 24 12 1098 7654 321 11 23 22 19 20 21 16 17 18 15 14 so gnd hs3 hs1 nc hs0 hs2 gnd fsi vdd si sclk cs rst wake fs in3 in2 temp in1 in0 csns gnd vpwr transparent top view material: single layer printed circuit board fr4, 1.6 mm thickness cu traces, 0.07 mm thickness outline: 80 mm x 100 mm board area, including edge connector for thermal testing area a : cu heat-spreading areas on board surface ambient conditions: natural convection, still air table 22. thermal resistance performance thermal resistance area a (mm 2 ) 1 = power chip, 2 = logic chip ( c/w) m = 1, n = 1 m = 1, n = 2 m = 2, n = 1 m = 2, n = 2 r ja mn 051 38 60 300 43 32 55 600 41 30 55 analog integrated circuit device data 36 freescale semiconductor 33580 additional documentation thermal addendum (rev 3.0) figure 13. stead state thermal resistance figure 14. transient thermal resistance 25.000 30.000 35.000 40.000 45.000 50.000 55.000 60.000 65.000 0 100 200 300 400 500 600 rja 11 rja 12=rja 21 rja 22 r ja11 r ja11= r ja21 r ja22 r ja11 r ja22 r ja11= r ja11 0.1 1 10 100 1.00e-06 1.00e-04 1.00e-02 1.00e+00 1.00e+02 1.00e+04 rja11 rja12=rja21 rja22 analog integrated circuit device data freescale semiconductor 37 33580 revision history revision history revision date description of changes 2.0 02/2006 ? implemented revision history page ? converted to freescale format ? added thermal addendum 3.0 05/2006 ? added b to the part number ordering information. ? minor drawing correction to figure 1 ? number changes to selectable output current and programmable watchdog in figure 2 ? changed temperature feedback min, typ, & max in the static electical characteristics ? changed max limit on overcurrent low detection blanking time for oclt[1:0] : 11 in the dynamic electrical characteristics ? minor corrections in figure 7, input timing switching characteristics ? added the sentence ?it is recommended to di sable the open load detection circuitry in case of permanent disconnected load.? to open load fault (non-latching) ? changed resistor value for the spi inputs from 1 k to 10 k in the typical applications ? updated the drawings and version on package dimensions ? made correction to the 33580 simplified internal block diagram on the hso mosfet. 4.0 6/2006 ? changed note 11 from guaranteed by desig n to guaranteed by process monitoring ? modified output turn on delay times on page 11 5.0 9/2006 ? adjusted numbers on see output rising fast slew rate a (dicr d3 = 1) (19) on page 10 and see output falling slow slew rate a (dicr d3 = 0) (19) on page 10 ? made additions and corrections to see typical applications on page 28 ? made changes to thermal addendum (rev 3.0) relating to figure 12 , table 22, thermal resistance performance , figure 13 , and figure 14 6.0 4/2007 ? changed the package type from 98arl10596d to 98art10510d ? removed pc33580bpna/r2, and added MC33580bapna/r2 MC33580 rev. 6.0 4/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 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